Our niche areas of research and interests lie in Embedded Systems, Digital Design, and Reconfigurable Computing . Our other areas of expertise include: Partial and dynamic reconfiguration on FPGAs, special-purpose architectures, hardware-software co-design, ASIC/FPGA-based architectures and techniques; System-on-Chip (SoC) Design; Computer Architecture; Hardware acceleration techniques, architectures, and methodologies for various application domains including edge computing, data mining/analytics, machine learning and deep learning, control systems including model predictive control algorithms for battery management systems for electric vehicles, bioinformatics including genetic algorithms for sequence alignment; Hardware security including security and cryptography on FPGAs; Hardware Architectures for Reservoir Computing and Neuromorphic Computing; Multi-ported memory architectures for FPGAs.
Our research on "Highly Adaptive Architectures for Edge Computing" is featured in our UCCS Communique News. Link to this news article.
Funded by National Science Foundation (NSF) from January 2022. NSF Award Abstract # 2138581.
In the Internet of Things (IoT) era, cloud infrastructure alone will not suffice to process and analyze the enormous amount of data being generated from various sensors/devices distributed throughout networks such as smart girds, smart homes, and autonomous vehicles. Traditional cloud infrastructure faces serious challenges when transmitting, processing, and analyzing this enormous amount of data, including: insufficient bandwidth, high latency, unsatisfactory real-time response, high power consumption, and privacy protection issues. Edge computing is emerging as a complementary solution to address the aforementioned issues of cloud infrastructure. However, edge computing is still in its infancy. Also, applications running at the edges of the networks are becoming more complex requiring more processing power. Existing algorithms/techniques for edge applications and conventional computing platforms utilized will not suffice to process and analyze this ever-increasing data and to handle the associated computational complexity, efficiently and effectively. Hence, innovative solutions are needed to propel the edge computing from its infancy, in order to support compute/data-intensive applications on next-gen edge-computing platforms that are heterogenous in nature.
To facilitate this endeavor, the main research objective of this project is to create an efficient and highly adaptive framework (comprising models, architectures, methodologies, and prototypes) to support and accelerate real-time processing of compute and data intensive applications (including data analytics/mining) on next-gen edge-computing platforms. Our unique framework will dramatically reduce the communication overhead and response latency of the corresponding networks and cloud infrastructure, and will enhance the performance and scalability of the systems. Due to adaptive traits, our solutions can be configured and utilized for broad range of edge applications, and will not be limited to specific application. Also, as an integral part of this research project, we will develop a graduate program in embedded and digital systems domains for both the doctoral and master’s students, since there is a significant demand for research and teaching in these domains in Colorado Springs, due to the high-tech companies in the vicinity. This graduate program will help us to attract and engage many graduate students in embedded/digital systems research, and will strengthen our research quality and output, in addition to producing highly qualified personnel to satisfy the growing demand of industry and academia in these domains.
My PhD student Mokhles Mohsin is currently working on this project.
Partially funded by UCCS Research ADVANCEment Grant
With the advent of IoT era, intelligent embedded systems (IES) will soon be the norm in many real-world applications such as smart homes, smart grids, and autonomous vehicles. Future IES will require encompassing self-aware traits, which in turn will enable them to be perceptive of their external environment and adapt their behavior to cater to highly dynamic natural environment. Since IES comprise both aspects of embedded and intelligent computing, creating hardware/software architectures/techniques, while providing the required intelligent, considering the constraints associated with embedded devices such as stringent area and power limitations, and dependability and real-time requirements, will be a challenging endeavor. Sophisticated machine learning (ML) models coupled with state-of-the-art dynamic reconfiguration techniques would certainly benefit future IES, in order to provide and enhance the required self-aware traits, such as self-adaptive, self-healing/correcting, self-learning, and self-optimizing attributes. Our analysis illustrate that low-cost Filed Programmable Gate Arrays (FPGAs) are one of the best avenues to create IES, not only because these FPGAs provide high performance, low power, and area efficiency but also many dynamic reconfiguration capabilities. Our investigation on existing research revealed that although there are some works on incorporating ML models into embedded systems designs, there are no existing integrated solutions that merge several techniques, including ML, dynamic reconfiguration, and optimization, to address many challenges involved in creating truly intelligent embedded systems for real-world scenarios.
Considering the aforementioned, the main research objective of this proposal is to harness the power of ML models coupled with dynamic reconfiguration and optimization techniques, in order to compose highly adaptive and intelligent embedded systems, consisting of many self-aware traits, on FPGAs.
My PhD student Shivani Sharma is currently working on this project.
One of our main research focuses is to investigate and create embedded and reconfigurable computing solutions for data mining/analytics on mobile and portable devices. Especially with the proliferation of embedded computing, a wide variety of applications are becoming common on these devices. This has inevitably led to research and investigation into lean code and small footprint hardware and software architectures for mobile and embedded devices. The major design constraints of these devices include stringent area and power limitations; high speedup, reduced cost and time-to-market, requirements. Data mining/analytics, which includes data analysis and processing, is one of many applications/tasks that are becoming common on mobile and embedded devices. Many of today's data mining tasks are becoming more complex (compute and data intensive), requiring more processing power. These constraints and requirements pose serious challenges to the embedded system designers.
Most of the existing architectures for data mining/analytics are processor-based software-only designs, and are typically designed for general-purpose computers; thus, as is, can not be executed directly on resource-constrained embedded devices. To satisfy these constraints/requirements, it is imperative to incorporate some special-purpose hardware architectures into embedded systems designs, which provides superior speed performance, lower power consumption, and area efficiency compared to the general-purpose microprocessors or processor-based designs. In addition, reconfigurable computing systems are desirable, particularly in situations, where all the computation circuitry does not fit into the chip simultaneously. These systems have similar advantages as special-purpose hardware, and have added advantages: single chip to perform various computations, flexible computing platform, and reduced time-to-market. In this research work, we are investigating special-purpose and reconfigurable hardware architectures to support and accelerate data mining/analytics applications on mobile and embedded devices, considering the associated constraints and requirements.In this domain, We are also investigating new design methodologies, including dynamic reconfigurable techniques, to enhance the reconfiguration flow.
Several graduate students were working on this project.
Information - coming soon.
My PhD student Muhammad Ali Khaliq and My Post-Doctoral Researcher Raghavendra Kumar are currently working on this project.
With the proliferation of wireless technology, software-defined radio (SDR) and cognitive radio (CR) concepts are becoming imperative in communication infrastructures. While SDR features have been incorporated into wireless systems, the true benefits of CR have not been fully exploited. The challenges/gaps in creating a truly cognitive CR/SDR system, include lack of: (1) reconfigurable mechanisms to configure CR/SDR for real-time adaptation; (2) learning techniques impeding proper sensing and resource allocation for spectrum utilization; (3) dedicated reconfigurable architectures for receiver/transmitter blocks. Also, there is a trend towards integrating dynamic partial reconfigurable (DPR) architectures and machine learning (ML) techniques into CR/SDR systems. However, an integrated solution, that merges several techniques (e.g., ML, DPR, optimization) to address many challenges in CR/SDR systems, does not exist yet. To address the above challenges and knowledge-gaps, we will create a flexible, agile, and intelligent cognitive radio architecture called ORACLE. For our ORACLE architecture, we will harness ML algorithms to optimize the dynamic reconfiguration of CR devices, while also taking into consideration that the spectrum and modulation agility needed in CR devices require purpose-built flexible transceiver structures, which enables fast run-time reconfiguration. This is a joint venture, between USA and Finland, which will consolidate the multifaceted expertise needed to accomplish the research goals, which in turn will lead to creating a truly cognitive system, encompassing self-aware traits, especially self-learning, self-adaptive, and self-management traits. We will demonstrate the desired outcomes of our ORACLE architecture using FPGA-based prototyping.
Embedded systems are becoming the cornerstone of many IoT-enabled cyber-physical systems (CPS), such as intelligent transportation and smart health. However, in IoT-enabled CPS, embedded systems are especially vulnerable to cyberattacks, not only due to the connectivity to the Internet and the utilization of off-the-shelf solutions, but also due to the associated constraints and typical remote operations of embedded devices, which in turn could compromise the major cybersecurity goals (confidentiality, integrity, and availability) of these systems. Hence, important challenges are: how to design embedded systems in such a way to ensure that cybersecurity goals are preserved in aforementioned scenarios; and how to incorporate security measures to highly-constrained embedded devices, efficiently and effectively, without compromising the integrity of IoT-enabled CPS' applications running on these devices. Our investigations revealed that hardware-based security mechanisms provide many advantages, especially to improve the security of embedded systems for IoT-enabled CPS, compared to software-based ones. In this research work, we will investigate and introduce novel, unique, and efficient hardware-based (or hardware-assisted) cybersecurity for embedded systems to address the major challenges discussed above. Furthermore, we will investigate and incorporate suitable machine learning (ML) techniques to our proposed hardware-based security mechanisms to further improve the security of embedded systems.
Partially funded by UCCS Cybersecurity Seed Grant.
In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA's many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device's security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency.
Initially, we introduced novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices.
My PhD student Arkan Alkamil worked on this project.
In the era of smart and autonomous systems, machine learning is becoming the cornerstone of these systems. Machine learning, a subset of artificial intelligence, is being incorporated into various fields such as medical wearables in healthcare and smart cars in transportation. Since most of these systems are typically realized on embedded devices, many machine learning applications are becoming common on these devices. However, embedded devices have many constraints and requirements: stringent area and power, increased speedup, and reduced cost and time-to-market. Furthermore, today's machine learning techniques/algorithms are becoming increasingly complex requiring more processing power. Also, these systems require real-time processing and analysis, in order to make dynamic decisions. Consequently, new architectures and techniques are required to support and accelerate machine learning applications on resource-constrained embedded devices. Our previous analysis illustrated that FPGAs are currently the most promising avenue to support compute/data-intensive applications, such as machine learning, on highly constrained embedded devices, due to FPGA’s many attractive features. In this research work, our intention is to create customized and optimized FPGA-based hardware architectures and techniques for machine learning applications on embedded devices, considering the constraints associated with these devices, as well as the requirements of these applications.
Machine learning algorithms can be categorized into supervised learning (classification) and unsupervised learning (clustering). Among many classification algorithms, Support Vector Machine (SVM) classifier is one of the most commonly used machine learning algorithms.By incorporating convex optimization technique to the SVM classifier, we can further enhance the accuracy and classification process of the SVM by finding the optimal solution. Hence, initially, we focused on the convex optimization (CO)-based SVM classifier, as a case study; and proposed generic, parameterized, and scalable FPGA-based hardware accelerators for CO-based SVM.
My PhD student Srikanth Ramadurgam was working on this project.
Partially funded by UCCS CRCW Grant.
With the ever-growing concerns about carbon emissions and air pollution throughout the world, Electric vehicles (EVs) are one of the most viable options for clean transportation. EVs are typically powered by a battery pack such as Lithium-ion, which is created from a large number of individual cells. Hence, efficient battery technology is imperative for the adoption of clean energy automotive solutions.In addition, efficient battery technology extends the useful life of the battery as well as providing provides improved performance to fossil fuel technology. To enhance the durability and prolong the useful life of the battery pack, it is imperative to monitor and control the battery packs at the cell-level. Model predictive control (MPC) is an effective way to operate battery management systems (BMS) at their maximum capability, while maintaining the safety requirements. MPC is a feasible technique for cell-level monitoring and controlling of the battery packs. Typically, for the batteries, MPC depends on two main mathematical models: the equiva-lent circuit model (ECM) and the physics-based model (PBM). Using the PBM of the battery allows the control system to operate on the chemical and physical process of the battery. Since these processes are internal to the battery and are physically unobservable, the extended Kalman filter (EKF) serves as a virtual observer that can monitor the physical and chemical properties that are otherwise unobservable. These three methods (i.e., PBM, EKF, and MPC) together can prolong the useful life of the battery, especially for Li-ion batteries. This capability is not limited to the automotive industry: any real-world smart application can benefit from a portable/mobile efficient BMS, compelling these systems to be executed on resource-constrained embedded devices. Furthermore, the intrinsic adaptive control process of the PBM is uniquely suited for smart systems and smart technology. However, the sheer computa-tional complexity of PBM for MPC and EKF prevents it from being realized on highly constrained embedded devices. In this research work, we introduced a novel, unique, customized, and optimized embedded hardware and software architectures for the MPC algorithms for battery cell managements, specifically on embedded devices, by addressing the computational complexity of PBM.
My PhD student Anne K. Madsen was working on this project.
The rapid growth of cyber physical systems (CPS) and the Internet of Things (IoT) are placing increasing demand on the internet and cloud computing infrastructure. Many mobile devices and systems off-load computationally expensive computing to cloud resources to achieve physical performance objectives of size and power while attempting to meet user requirements in terms of speed and responsiveness. As the number of CPS and IoT are only expected to increase, eventually the demand will exceed the internet and cloud resources. Prime examples of complex cyber physical systems with constrained resources are unmanned vehicles and smart cars. These systems incorporate the model predictive control (MPC) for path planning and collision avoidance; machine learning for object identification, human driving patterns, or frequency usage; and data mining techniques to gather and analyze critical data. To create smart devices while reducing communication and cloud dependency, the computing capability and responsiveness of the available platforms needs to increase, ideally without increasing the size or power consumption. Our objective of this research is to design an FPGA-based systems-on-chip that incorporates a microcontroller and hardware accelerators for control, data mining, and machine learning to support cyber physical systems development. In this research work, we will use hardware software co-design approach to create a configurable platform that can be accessed through an onboard microcontroller. Our focus is on the control and integration aspect of the platform design. Thus far, we have proposed an efficient MPC algorithm on FPGA. Future work will include the investigation and creation of theoretically more efficient MPC algorithms. A reconfigurable design will be proposed to reduce area. The data mining and machine learning modules will be developed and integrated into the proposed computing platform.
With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multi-ported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time.
To faciliate this endeavor, we initially introduced unique and efficient uni-directional multi-ported memories, which were created to significantly reduce the design and routing complexity. Later, we introduced novel, unique, and efficient bi-directional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed uni/bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency.
My PhD student S. Navid Shahrouzi was working on this project.
Partially funded by UCCS Cybersecurity Seed Grant.
Raman spectroscopy is a sensitive, versatile, and reliable analytical tool that is currently used in a wide range of public safety applications, including the detection of explosives, chemical warfare agents, drugs, and agricultural contaminants, as well as for water and food quality monitoring. Realizing its full potential requires a spectrometer with sufficient resolution to acquire the spectra and skilled personnel or Machine Learning (ML) techniques to analyze the obtained data/results. However, the lack of technical capabilities in remote areas with limited resources can delay these analyses, which in turn could lead to fatalities. To address this issue, in this research work, we propose an affordable smartphone-sized solution. We have two objectives: Firstly, we will extend our ML framework, which currently works efficiently on a desktop computer, to an embedded microprocessor/microcontroller and embedded and reconfigurable hardware to make it smartphone-sized and easy to use. Secondly, since existing portable Raman spectrometers available on the market are quite expensive, we will create an affordable solution using a smartphone camera (around $50 plus smartphone price) and couple it with our portable/embedded ML system. Our proposed solution will enable us to lay the foundation for applying for external grants and seeking paths to commercialization. This is a joint project with the Physics Department at UCCS.
Information - coming soon.
For more information on current research, see the publications and see the students.
Last updated on 15th June 2024